The present invention relates generally to microelectronic devices, and specifically to electronic fuse vias formed as part of interconnect structures.
A fuse is a structure that is blown in accordance with a suitable electrical current. For example, an electrical current is provided through the fuse to eventually cause the fuse to blow and create an open circuit. Programming refers to intentionally blowing a fuse and creating the open circuit. In integrated circuitry memory devices, fuses can be used for activating redundancy in memory chips and for programming functions and codes in logic chips. Specifically, dynamic random access memory (DRAM) and static random access memory (SRAM) may employ fuses for such purposes.
Electronic fuses (e-fuses) can also be used to prevent decreased chip yield caused by random defects generated in the manufacturing process. Moreover, e-fuses provide for future customization of a standardized chip design. For example, e-fuses may provide for a variety of voltage options, packaging pin out options, or any other options desired by the manufacturer to be employed prior to the final processing. These customization possibilities make it easier to use one basic design for several different end products and help increase chip yield. Previously, e-fuses were incorporated at the silicon level of microelectronic devices, but as devices continue to scale down, silicon-level e-fuses become increasing impractical due to the maximum allowable current through the silicon level.
To address this problem, e-fuses may be incorporated into back-end-of-the-line (BEOL) structures such as metal vias to take advantage of electromigration (EM) effects to blow and create the open circuit. For example, EM can be defined as the transport of material caused by the gradual movement of ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. In e-fuses that take advantage of EM effects, such transport of material caused by the gradual movement of ions can produce voids which cause the e-fuse to blow and create the open circuit.
However, EM effects can be difficult to control, resulting in the formation of voids outside of the desired fuse region, for example in metal lines connected to an e-fuse via. Accordingly, a fuse via that will reliably blow within the via without causing damage to the surrounding BEOL structures is desirable. Referring to FIG. 1, a structure 10 may represent a typical e-fuse via structure in which the EM failure mode of the e-fuse via structure after programming is depicted. The structure 10 may include a first metallization level 20, including a metal line 25, and a second metallization level 30 above the first metallization level 20. The second metallization level 30 may include a metal line 33 and an e-fuse via 36, which joins the metal line 25 and the metal line 33. In other embodiments, metal lines 25 and 33 may be any other known back-end metal structure, such as vias. The first metallization level 20 may further include a first insulator layer 21 and a capping layer (not shown) below first insulator layer 21, and the second metallization level 30 may further include a second insulator layer 31 and a capping layer 32 separating the features of the first metallization level 20 from the second insulator layer 31 except where intended (e.g., where the metal line 25 joins the e-fuse via 36). It should be noted that while this application refers to a first metallization level and a second metallization level, microelectronic devices may have many metallization levels. Therefore, as used in this application, first metallization may refer to any metallization level x, while second metallization level may refer to any metallization level x+1 above metallization level x.
During programming, voids 41-43 may form in the e-fuse via 36, metal line 25, and metal line 33, respectively. However, programming will ideally cause only the e-fuse via 36 to blow (i.e. cause voids capable of substantially increasing electrical resistance to form) while maintaining the integrity of all surrounding circuits. For example, void formation in metal lines 25 and 33 may result in undesirable damage to adjacent capping layers (e.g. the capping layer 32, and a not-shown capping layer above the second insulator layer 31). Voids in metal lines 25 and 33 may also cause damage to circuits other than the one targeted during programming. Further, the location of the void formation may affect the amount of current required to blow the e-fuse. Generally, higher currents may be required to form a larger void, therefore higher currents may be necessary when the void forms in the connected lines rather than in the fuse via. Further, it is possible in some cases for the void 41 to not fully span the e-fuse via 36 as depicted. In such cases, it is possible for the resistance across the via to increase, but not to the degree required by the programming. Therefore, the performance and reliability of e-fuses may be improved by encouraging voids to predictably form only in the e-fuse via (e.g., the void 41 in the e-fuse via 36) and not in the connecting metal structures (e.g. metal lines 25 and 33), while also ensuring complete failure of the e-fuse via.